In FPGA design, sometimes the previously written design code is used. It is usually better to customize these similar reusable modules independently into an IP block for future needs. The design process is as follows:

Step 1: Write a module as usual for building engineering design. Take the lighting of LED as an example (starting from everything), the code is as follows (it is a frequency division 1000hz program, the output looks at the LED display):

module led(
           input clk,
		   input key,
		   output reg clk_div
    );
reg [4:0] cnt1;
reg [15:0] cnt2;
reg [9:0] cnt3;
reg clk_div1;
reg clk_div2;
reg clk_div3;

initial
begin
  cnt1 = 5'd0;
  cnt2 = 16'd0;
  cnt3 = 10'd0;
  clk_div1 = 0;
  clk_div2 = 0;
  clk_div3 = 0;
end

 always @(posedge clk) //200MHz frequency division to 10MHz
begin
   if(cnt1 == 9)
	begin
	   clk_div1 <= ~clk_div1;
		cnt1 <= 5'd0;
	end
	else
	   cnt1 <= cnt1 + 1;
end 
 always @(posedge clk_div1) //10MHz frequency division to 1000Hz
begin
   if(cnt2 == 4999)
	begin
	   clk_div2 <= ~clk_div2;
		cnt2 <= 16'd0;
	end
	else
	   cnt2 <= cnt2 + 1;
end

always @(posedge clk_div2)
begin
   if(key)
	  clk_div <= 1;
	else
	  clk_div <= 0;
end


endmodule

Set the synthesis option, and IO buf cannot be added in the synthesis process (taking into account the interface with external modules). In the comprehensive settings, -iobuf is not checked, -iob is NO, as shown in the figure below

Step 2: Make a blockbox module (that is, a wrapper package design of an IP core), the wrapper program is as follows:

module led(
       input clk,
	   input key,
       output reg clk_div
    );

endmodule //only declare the port

 

The third step, to use this IP, you need to add the blackbox of the second part to the project as a v file, call this module, and then add the led.ngc file to the project folder.

module top(
    input clk,
	input key,
	output valid,
	output led
    );

assign valid = (led = 1'b1) ? 1:1'b0;

 led U1 //Call led IP core
(
    .clk(clk),
	.key(key),
	.clk_div(led)
);
endmodule

Project engineering file, note: be sure to add the led Wrapper program to the project

Comprehensive success

At this point, you can generate IP cores from your own HDL code to avoid rewriting or adding when you need to use duplicate codes.