HDL/FPGA study notes twenty-four: the use of Vivado ROM IP core

1. ROM IP core configuration

ROM is much simpler than the RAM mentioned earlier, because it only has a port for reading data and no port for writing data. However, it can still be configured as a single port or dual port, where the dual port refers to the port for reading data. Because it's relatively simple, I won't introduce too much here. The following is the configuration of the ROM IP core of my experiment:

1. Find ROM IP core

As you can see, it is actually the same as the previous RAM.

2. Choose single-port ROM

3. Set the data bit width and depth

4. Initialize ROM

Used here iscoeFile, the content of the file is as follows:

MEMORY_INITIALIZATION_RADIX=16; //The data format indicating the ROM content is hexadecimal
MEMORY_INITIALIZATION_VECTOR= 
11,
22,
33,
44,
55,
66,
77,
88,
99,
aa,
bb,
cc,
dd,
ee,
ff,
00,
a1,
a2,
a3,
a4,
a5,
a6,
a7,
a8,
b1,
b2,
b3,
b4,
b5,
b6,
b7,
 b8; //Each data is separated by a comma or a space or a newline character, and a semicolon is added after the last data

2. Examples

In this example, we simply read the data in the ROM one by one, and the read data address is incremented.

1. RTL code

`timescale 1ns / 1ps

module rom_test(
	input sys_clk,	//50MHz clock
	input rst_n		//Reset, active low
    );

wire [7:0] rom_data;	  //ROM read data
reg	 [4:0] rom_addr;      //ROM input address 

//Generate ROM address to read data
always @ (posedge sys_clk or negedge rst_n)
begin
    if(!rst_n)
        rom_addr <= 10'd0;
    else
        rom_addr <= rom_addr+1'b1;
end        
//Instantiate ROM
rom_ip rom_ip_inst
(
    .clka   (sys_clk    ),      //inoput clka
    .addra  (rom_addr   ),      //input [4:0] addra
    .douta  (rom_data   )       //output [7:0] douta
);
endmodule

2. Simulation program

`timescale 1ns / 1ps

module vtf_rom_tb;
// Inputs
reg sys_clk;
reg rst_n;


// Instantiate the Unit Under Test (UUT)
rom_test uut (
	.sys_clk	(sys_clk), 		
	.rst_n		(rst_n)
);

initial 
begin
	// Initialize Inputs
	sys_clk = 0;
	rst_n = 0;

	// Wait 100 ns for global reset to finish
	#100;
      rst_n = 1;       

 end

always #10 sys_clk = ~ sys_clk;   //20ns a period, generate 50MHz clock source
   
endmodule

3. Simulation results

It can be seen that the read data and the abovecoeThe content in the file is the same, indicating that the experiment was successful! ! !

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