This blog post reference: "Large-Scale Logic Design Guide" is very helpful for writing standard code and cultivating a good code style.

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wire and register

• A reg variable can only be assigned in one always statement;

This explanation is very important. If this is not satisfied, maybe there is no problem in the simulation, but it will definitely appear during the synthesis and cannot be synthesized. I have made this mistake many times.

I once wrote a blog that specifically said:There is no problem to perform functional simulation under Modelsim, but a comprehensive error is reported in ISE, how to solve it?

• The definition of the significant bits of the vector is generally from large to small.

Although the standard does not enforce this, it is more standardized and easier to read.

Expressions

• Use parentheses to indicate the priority of execution;

This is easier to understand. Although the Verilog HDL language has its own priority, the use of parentheses to indicate priority is clearer and more meaningful to the reader.

For example: if ((a> b) && (c> d)) ......

It is better than the following expression:

if (a> b && c> d), although the two have the same effect.

 

• Instead of repeating expressions multiple times with a function, a frequently used set of descriptions can be written to a task.

If statement

• When comparing vectors, the compared vectors must be equal;

When comparing vectors, Verilog will zero-extend vectors with a small number of bits to match their lengths, and its automatic expansion is implicit. It is recommended to use display expansion. This rule also applies to the comparison of vectors and constants.

E.g:

reg [7:0] a;

reg [3:0] b;

...

if( a == {4'b0, b} ) begin

...

end

if( a == 8'b0 ) begin

...

end

 

• Each if has an else corresponding to it;

When doing hardware design, it is often required to perform an action when the condition is true, and perform another action when the condition is false. Even if the condition is false, it is impossible to occur, there must be an else statement, which can be an empty Statement.

If there is no else statement, the synthesized logic may be different from the logic at the RTL level. (What does this sentence mean? If there is no else statement, the synthesis tool may synthesize something that you do not want to appear, such as synthesizing a latch. You can not use a latch, but it is because there is no else Statement, and the latch is synthesized, which not only affects the overall performance of the circuit, but also causes waste of resources.)

E.g:

always @(Cond)
begin
    if(Cond)
        DataOut <= DataIn; // The else statement is missing
end

The above statement DataOut will be integrated into a latch.

• Should pay attention to the priority of if ... else if ... else

The above statement has priority, if has the highest priority, else if follows, else last.

• If the variable is incompletely assigned in an if ... else or case statement, the variable should be given a default value, namely:

V1 = 2'b00; //default
V2 = 2'b00;
v3 = 2'b00;

if(a == b) begin
    V1 = 2'b01;
    V2 = 2'b10; //V3 is not assigned

end

else if(a == c) begin
    V2 = 2'b10;
    V3 = 2'b11; //V1 is not assigned
end

else ;

The above meaning is that if the variable is not all assigned in the statement, then the variable should be given a default value at the beginning, otherwise its value is unpredictable.

case statement

• The case is usually integrated into a first-level multiplexer (the right part of the figure), and if ... else ... is integrated into multiple multiplexers with priority coding in series, as shown in the left part of the figure. The case statement is usually faster than the if statement, and the structure of the priority encoder is only used when the signal arrives in sequence. Conditional assignment statements can also be synthesized into multiplexers, and case statement simulation is faster than conditional assignment statements.

 

• All cases should have a default, allowing empty statements, namely:

case

...

default: ;

endcase

 

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This blog post is here for the time being. Of course, there are still many places to pay attention to, and we will continue to update it in the future. The update includes modifications and additions to this blog, which are explained based on actual inspections.

For example: I haven't said much about the following sentence because I don't know it yet. In the past circuit design, functions and tasks were rarely used, so you have to learn and then practice.

Instead of repeating expressions multiple times with a function, a frequently used set of descriptions can be written to a task.

[Verilog HDL] A brief introduction to functions and tasks