Verilog HDL (1)
tags: verilog
Verilog HDL language foundation
Basic syntax rules
1, identifier
be careful:
1 case sensitive
2 can't start with numbers, "$" etc.
3 Transfer Identifier: Use \ as the beginning, with a blank character (space, tab, backbill end)
reg clk;
reg \clk ;
These two are the same
2, interval
1 space character (\ b)
2TAB button (\ T)
3 wrap (\ n)
3, constant and its representation method
| Integer constant constant | Real number constant | String type constant |
|---|---|---|
| Integrated | Not integrated, used for logic simulation | Not integrated, used for logic simulation |
1 Commonly used representation of the integer type constant:
- Decimal form
Example: 30 - Expressed in the form of a base (format: <bit wide> ")> <value>)
Example: 32'd47
2 Realism in Verilog:
Example: 0.1, 0.52
Verilog language can automatically convert real numbers to integers
3 character string production:
Example: "Hello Word!"
Verilog will convert a string into a string 8bitascii value of unsigned integer.
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