Verilog HDL language design framework and code style!

Module

Module is the main body written by the Verilog code. So, what is the content of this subject is worth a newcomer. There are a lot of content in a module. Here is a complete module reference model (this model is for reference only).
Note: Use this module basically no problem, rest assured!

Complete Module Reference Model:

`define AAAA aaaa       // Macro definition
`include"abc.v"		   // file contain
`timescale 1ns/1ns    // Time scale definition
//-----------------------------------
module main (Complete port list);	 // Module declaration, port list should be complete
input	[width]	a;			// Enter, the bit width output
output	[width]	b1;
output	[width]	b2;
inout	[width]	c;
//---------------------------------------
// Wire [Width] B1; // B1 is the wire mesh output, which can be omitted
reg		[width]	b2;		// B2 is the register output, commonly used for timing circuits

reg		[width]	e;		// vector used within the module
wire	[width]	f;		// Connection line used within the module
integer	[width]	g;		// integer type
//-----------------------------------
parameter	H=Numerical value;		// Parameter declaration
//------------------------------------
// Timing logic circuit design, use non-block assignment
always @ (Posedge signal or negedeg signal)
begin		
	b<=a;
end
//-------------------------------------
/ / Combined logic design, use blocking assignment
always @ (signal)
begin
	b=a;
end
//-------------------------------------
// Simple or logical clear combination logic, this is a data stream statement
assign = b=~a;
//-------------------------------------
// Gate-level call
and and1 (b,a,~a);
//------------------------------------
// Module instantiate, improve module readability
ZZZ my_zzz (Port connection);

endmodule 

All Module design is taken from a certain part of the above template. If the code (verification) code is written can be moved by this module; for a long time, you can write a beautiful code (of course, as long as you write the code to see others. It can be comfortable, the language is flexible.)

Code style:

The code style is not to say how I want to write, I feel that this is good, I want to have a self-contained (why not go to the sky). Style, in fact, to some extent, everyone's "habits", this "habit" is to help designers (new hands, for example, I) minimize unnecessary errors. For example, everyone says that watermelon and mutton can't eat together. That is not believed, you will eat it; it is still diarrhea, it is uncomfortable. The code style is as much as possible to make you slightly tellers or not diarrhea.
Common code style is as follows:

1, multiple drive problems

code show as below:

reg clk,rst;
reg [1:0] out,a,s;

always @ (posedge clk)
if (rst)
out=2'b00;
......

always @ (posedge clk)
if (a==0)
out=2'b11;
......

In this code, if you don't understand the number of digital circuits, you may think so. Each time you go to the clock rising edge, if the reset signal is valid, the output is 0; if A == 0 outputs 11. It seems clear that it has multiple drivers in this. In the integrated circuit, the assignment of a signal will only occur in an alway; if the code is as described above, this circuit will try to assign a value of the same output, which will "collide".
This situation is that we did not correct the idea to circuit. Design ideas is not "in these cases, what is output, but" what should be output in these cases ", we must imagine yourself is a circuit (if you make a chip, imagine yourself is a chip) .

2, sensitive list is incomplete

For combination circuits, in @ boot sensitive lists must contain complete sensitive lists. For timing circuits, @-sensitive events do not all become asynchronous circuits, but the design of asynchronous circuits is not supported (in the company, design person is useless).
If the sensitive list is incomplete, a logical error can cause a logic error. There may even be a latch. such as:

always @ (a)	// sensitive list does not have B
c=a~^b;

B changes that the Always structure changes, which is a controlled latch.
The modified code is as follows:

always @ (a or b)
c=a~^b;

3, IF and ELSE are inconsistent

4, the CASE statement lacks Default

5, combination and timing mixing design (this is nonsense)

Note:

The REG output does not mean that the output must be a REG type. The output can only be said that most of the REG type.

All above are some of pre-experience, do not make this low-level error. Of course, you can deliberately write a few such code to play. However, you will find that even if you make mistakes, you will get the results you want, this is to thank your compiler and integrated. Don't see God.
There are also some small habits, help, do not need to be used.
1, using parameterized design as much as possible; easy to modify, the parameter of the top module affects the sub-module.
2, do not use Tab, use spaces; when the code is transferred, the format will not be wrong, the function does not have any problems, and it is still a kind of control.
3, only one-way annotation can only be used in the design, and the annotation amount should account for more than 35% of the design code; people will forget to make memories.

to sum up:

This blog content belongs to it repeatedly. Like tea, you will slowly reflect the fun in it.

I feel:

no