The sequence detector is one of the very common designs in sequential digital circuits. Its main function is to identify a specified sequence from the digital code stream.For example, after receiving a serial code (10010), the detector outputs the flag 1, otherwise, it outputs 0.

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In the "10010" sequence detector, there are 6 states, plus an Idle state, a total of 7 states. But you can first reduce the amount of Verilog code by simplifying the state. The initial state analysis is shown in the table below.

It can be seen that the state "Idle" and the state "0", "10010" under the same input, the next state is exactly the same as the output, so it can be reduced to a state, after all the states are simplified, the state is named and encoded .

Name the states of "Idle", "1", "10", "100", and "1001" respectively as "Idle", "S1", "S10", "S100", and "S1001". The Verilog program is as follows:

module seq_detector(seq,clk,rst,b);       // detector "10010"
input seq,clk,rst;
output b; 

reg b;
reg [4:0]state;

parameter Idle  = 5'b1_0000,
          S1    = 5'b0_1000,
          S10   = 5'b0_0100,
          S100  = 5'b0_0010,
          S1001 = 5'b0_0001;

always @(posedge clk or negedge rst)     //low active
  if (!rst) begin
              state <= Idle;
              b <= 0;
             end
  else 
      case(state)
     Idle: if( seq == 0)
              begin
                state <= Idle;
                b <= 0;
              end
           else
              begin
                state <= S1;
                b <= 0;
              end
 
     S1: if( seq == 0)
              begin
                state <= S10;
                b <= 0;
              end
           else
              begin
                state <= S1;
                b <= 0;
              end

     S10: if( seq == 0)
              begin
                state <= S100;
                b <= 0;
              end
           else
              begin
                state <= S1;
                b <= 0;
              end

     S100: if( seq == 0)
              begin
                state <= Idle;
                b <= 0;
              end
           else
              begin
                state <= S1001;
                b <= 0;
              end

     S1001: if( seq == 0)
              begin
                state <= Idle;
                b <= 1;
              end
           else
              begin
                state <= S1;
                b <= 0;
              end
      
      default state <= 5'bx;
    endcase
endmodule

The testbench files are as follows:

`timescale 1ns/1ns
`define halfperiod 20

module t;
reg clk,rst;
reg [23:0]data;
wire seq,b;
assign seq = data[23];

initial
  begin
    clk = 0;
    rst = 1;
    #2 rst = 0;
    #30 rst = 1;
    data = 20'b1100_1001_0000_1001_0100;
    #(`halfperiod * 1000)$stop;
  end

always #(`halfperiod) clk = ~clk;
always @(posedge clk)
         #2 data = {data[22:0],data[23]};

seq_detector m(.seq(seq), .clk(clk), .rst(rst), .b(b) );

endmodule

The results obtained through Modelsim simulation are as follows:

It can be seen that after seq occurs in the "10010" sequence, b can detect the input of the sequence and output a high level.