According to the provision of input vectors in the process of power analysis, the power estimation method can be divided into simulative and non-simulative methods (non-simulative):

1. The method of simulation is to simulate the circuit according to the large number of input vectors provided by the user, and utilize the power estimation tool to estimate the specific power value. This method only needs to simulate the time long enough, and the accuracy of the power consumption can be high. However, due to the limited time and memory requirements (for large-scale integrated circuits, it is possible to obtain a smaller-scale integrated circuit in a short period of time).
2. Non-empty methods first generate some information related to the circuit, which may be random, or it can be determined, and then passed through this information, such as information discussion, ATPG method, statistical method, etc. Non-emulation methods can improve the speed of power estimation, but the accuracy of power estimation is not simulated.

Synopsys' Tools Power Compiler is embedded in Design Compiler, is a comprehensive tool that can optimize the area, power consumption and timing. It mainly has two functions: First, it can automatically optimize the power consumption of the circuit, minimize it; second, power consumption before circuitry, so that the designer can better complete the power distribution plan, Complete the low power design of the circuit in a short period of time.

The process of implementing the gate-class power estimation with Power Compiler is as follows:

First, get the SAIF (Switching Activity Interchange Format) file;

Using Tools Power Compiler When you perform power estimation, you will use both format files for SAIF and VCD (Value Change Dump), which are all used to record flip messages for each node in the design. The SAIF file only saves the number of times each node has flipped, and the VCD file saves the time of each node that flips. Since the VCD format file records time information, it is much larger than the SAIF format file.

The accuracy of power estimation is mainly dependent on whether the flipping information of each node is reliable. Using Tools Power Compiler estimates power consumption When you read the SAIF file, you can get the flip information of each node. In the simulation tool, the designer uses the simulation program or the signal vector to make each device in the design, and record the total hop number in the SAIF file. SAIF format files can be generated by two ways:

1. Generate SAIF files by simulation

1) RTL simulation

As shown in the figure, the RTL simulation generates a flow chart that generates the SAIF format file, just add the simulation program after the TOGGLE_START, $ TOGGE_STOP, $ TOGGLE_START, $ TOGGLE_STOP, $ TOGGLE_START, $ TOGGLE_STOP, $ TOGGLE_START, $ TOGGLE_STOP, and TOGGLE_REPORT can be run.

A simple example is as follows:

initial begin 
    $set_toggle_region(design_test.design_top); 
    $toggle_start(); 
    ... .. / / omitted the test statement in Testbench 
    $toggle_stop(); 
    $toggle_report("design.saif",1.0e-12,"design_test"); 
    $finish; 
end

2) Gate-level simulation

The following figure shows a flow chart of the gate-level simulation generating SAIF format file. First read the design file in Design Compiler, generate forward SAIF files such as Forward.saif by command lib2saif. The SAIF file that generates the anti-target is then simulated by VCS. Before the simulation, TestBench needs to be added to the command required to add the RTL simulation to generate the SAIF format file, you must also add a command $ read_lib_saif (forward.saif) before $ set_toggle_region.

2, other file conversion

1) Convert VCD format files into SAIF format files with command VCD2SAIF.

2) Use the command fsdb2saif to convert the FSDB format file to the SAIF format file.

Second, Power Compiler reads in SAIF format file for power consumption estimation

After generating the SAIF format file, you can use the Power Compiler tool to perform power to estimate. The specific steps and the main scripts are as follows:

/ / ========= Read the design file in the Design Compiler =============
analyze -format verilog -library WORK /home/fxia/design/src/timescale.v 

analyze -format verilog -library WORK /home/fxia/design/src/design_defines.v 

 ... / / Other design documents 

analyze -format verilog -library WORK /home/fxia/design/src/design_top.v 

elaborate design_top -library WORK -architecture verilog 

set current_design design_top 

link

 / / ========= Define the clock and various constraints ==============

......

 // ========= Read the SAIF format file generated in front =============


read_saif -input design.saif -inst design_test/design_top


 / / ========= Power consumption report for generating design =============

report_power -analysis_effort high -verbose > $report/design_add_sig.power_rpt