IC design ram002_ECC verification principle basics
1. ECC verification basis
Ram's ECC verification is usually implemented based on the principle of Hamming code encoding. Using Hamming code encoding requires additional bits to store the check bits. ECC verification can only correct 1 bit, and cannot correct 2 bit or above data errors. Some multi-bit bit errors can be found.
2. Principle of RAM ECC verification implementation
As shown in the figure, the 1r1w ram is an example. cfg_32x119_ram_wrapper is a verilog code that directly calls the hierarchical ram_wrapper, representing a ram with a depth of 32 and a data bit width of 119 bits. ram_asic.v is the real ram IP. Among them, the 119 bit data bit width is tight. ECC calculation requires a 7 bit check bit, so the physical IP requires a minimum of 126 bit ram IP. Usually, the memory generation tool will have more clock frequency, depth bit width and other factors to segment the ram, so in this example, two 32x64 ram ips are used.
Before data_in is written to ram_asic module, a 7-bit ecc check bit will be generated through the ecc_gen module, and ram_asic will be written together with the data, where data_in[63:0] is written to the first ram_asic, {2’b0, ecc_in[6:0], and data_in[118:64]} is written to the second ram_asic. The data read from ram_asic will be checked by the ecc_out module, and the ecc_err_out alarm after verification is output.
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