LTR：Latency Tolerance Reporting


LTR is an optional feature specified in the PCIe protocol, which can be used to improve the power management efficiency of the system.


By LTR, the PCIe device can inform the system how much they can tolerate, as long as the system responds to the request asked by the PCIe device within this time. The system's power management policy can be optimized according to the information provided by the LTR. When the device is required, the system quickly responds to the request proposed by the device; when the device is not required, the system can delay a response to the device request, as long as it does not exceed the time specified in the device LTR message. For example, if the system receives the request from the device while the system is low, then the request will respond to this request, avoiding frequently waking up from the low power state.

LTR register

The Device Capability 2 register in the PCIe configuration space indicates whether the device supports LTR, as shown below:



The Device Control 2 register in the PCIE configuration space indicates whether the device enables LTR, as shown in the following figure:

The PCIe protocol stipulates that when the LTR of the PCIe device should be enabled, the equipment close to the root complex should be enabled. The endpoint LTR can only be enabled when the EndPoint connected root port and the intermediate Switch support and enable LTR.


In the same PCIe bus system, endpoints that support LTR and EndPoints that do not support LTR are intended.


If root port or switch receives LTR messages from EndPoint without supporting LTR or does not enable LTR, you should take it in accordance with UNSUPPORTED REQUEST.


It is recommended that endpoint sent the LTR message immediately after being enabled. At the same time, it is highly recommended that the LTR message sent within 500 US is not more than 2 unless the protocol requires this.


LTR information is to be sent to root complex. The downstream port of Root Complex may pick up a lot of Endpoint, and each endpoint will send LTR information. Root Complex selects the minimum value as the actual usage standard in all LTR information received.

2. LTR Message (LTR Message)

The LTR message format is shown below:



The LTR message includes two latency values: no-snoop latency and snoop latency. The same format is the same:

• Latency Value and Scale: These two parameters can be used in conjunction with Latency to 1 nanosecond ~ 34 seconds. If you set these two values ​​to 0, it means that any delay affects the device, so the system needs to respond to the request in the first time. For different request types, the significance of Latency is as follows:
  • For a read request, Latency means the start of the End ID from the read request TLP until the period of the first Completion TLP is received.
  • For the write request, Latency means starting from the ENDPOINT write request TLP to start until the endpoint can issue this period of the next write request. The write request will receive the impact of the Flow Control. For example, endpoint issues a write request, its upstream port (UPSTREAM) Credits (ROOT port or Switch) of CREDITS causes EndPoint to continue to send the next write request. Only endpoint received the opposite DLLP to inform it that after sufficient Credits, EndPoint will continue to send a new write request. In this scenario, Latency is sent from the END request from the first write request until this time is received from the STP identity that releases the DLLP of Credits.
• Requirement: Do you need latency value. Can be set to 0 or 1. For example, if the PCIe device does not issue a NO-SNOOP request or the NO-SNOOP request does not have a Latency demand, then the Requirement bit of the NO-Snoop Latency area in the LTR message can be set to 0. If the PCIe device A issues a LTR message, the device B accepts this message does not enable the LTR message or the device is lower than the power consumption, the device A needs to send a LTR message again, and put the message The Requirement bit is set to 0.

The images in this article are from MINDSHARE, INC Classic book "PCI Express Technology".

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