[VCS][UVM]UVM HDL Backdoor Access Setting
tags: Verifying engineers develop notes VCS SoC
UVM HDL Backdoor Access Setting
Foreword: In SOC verification, in order to improve the speed of compilation and simulation, we usually remove the option of debug_access+all. But doing this will cause a serious problem: UVM Backdoor Access will fail. So how can we guarantee both? This article will introduce a method.
1. Give Backdoor Access permissions to specify the specified Module through Module Name
First of all, you need to make a list to specify which module needs Backdoor access.
- soc_acc.tab
acc=frc,rw,wn:slave_dec
acc=frc,rw:bsc_reg_xaru- Come to eat this list in VCS compilation
-debug_access+pp -P ${PWA}/src/common/vcs/pli_table/soc_acc.tab- vcs option
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