How to generate fsdb waveform in verilog simulation?

There are many formats for verilog simulation waveforms, among which the standard format is VCD, which can be used as a cross-tool data exchange format. However, VCD itself is not compressed, which is usually larger. For pure digital simulation, there can be other waveform file formats as an alternative. For example, Synopsys' VPD format, and FSDB. fsdb is the waveform format of the verdi tool (acquired by synopsys). The ease of use of verdi is favored by the majority of digital engineers. This article introduces how to export fsdb waveforms. Take vcs+verilog as an example, other tools are similar.

Method 1: In the verilog file

Add the following statement in the test file (usually at the top level):

initial begin
     $fsdbDumpfile("xx.fsdb");
     $fsdbDumpvars(0,"top name");
end

The first parameter in the fsdbDumpvars function indicates the depth of the derived signal level, and 0 means all levels.
In addition, the -P parameter needs to be added to the vcs script. Take Makefile syntax as an example, such as:

NOVAS=${NOVAS_HOME}/share/PLI/VCS/LINUX64
novas_args=-P ${NOVAS}/novas.tab ${NOVAS}/pli.a
run:
	vcs -full64 -debug_pp ${novas_args} *.v -top TOP -l vcs.log
	./simv

Where NOVAS_HOME is your verdi installation directory.

Method 2: Use the do file

This method does not need to add dump syntax or functions to verilog.
only need to write a do file, such as:

fsdbDumpfile "dsss_decode.fsdb" 500
fsdbDumpvars 0 TOP "+all"
fsdbDumpon
run
fsdbDumpoff
quit

Simulation script (Makefile) does not require additional -P parameters, as follows:

run:
     vcs -full64 -debug_pp -top TOP ${SRC} -l vcs.log
     ./simv -ucli -do tb.do -l run.log

Does it look more concise? You can add other wave file export commands or other more complicated wave control commands in the do file at the same time. More convenient and flexible.

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