STM32F103 clock configuration source code learning record

After reading this recordAtomic Battleship EditionThe understanding of the clock configuration video is only used as a memo.

The clock configuration source code is in the file system_stm32f10x.c. The program first selects the system clock frequency SYSCLK you want by judging the type of f10 chip used. The chip system frequency I use is up to 72Mhz, and the chip capacity is a large-capacity type, so the choice after pre-compilation isSYSCLK_FREQ_72MHz 72000000。

The following code is useless in the clock configuration, but can be passed in the future programSystemCoreClockTo read the frequency of the system clock.

The following code uses macro definition to select the function to configure the system clock. The above function definesSYSCLK_FREQ_72MHz, so the program is executedvoid SetSysClockTo72 (void). Jump to this function

The following function is not important, just skip it

The three lines of code first say that the AHB bus clock is equal to the system clock, and then the APB2 clock is equal to the HCLK divide by one, and the APB1 clock is equal to the HCLK divide by two. The result isHCLK=72MHz,PCLK2=72MHz,PCLK1=36MHz.。It just happens to be the highest frequency allowed on the respective bus.

Look at the picture below and skip the code above it. The code under else is to set the phase-locked loop through the configuration register. The frequency from the phase-locked loop is 9 times the frequency of the external high-speed clock.

Finally, enable the phase-locked loop PLL. After the PLL is ready, use the PLL as the source of the system clock.

To understand the clock configuration source code, you must first understand the clock system block diagram. The two clock diagrams are similar, but the labels are slightly different.

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