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Introduction to state machine

The module design code is as follows:

The test platform is as follows:

Makefile simulation script VCS + VERDI

Run.tcl file

Simulation waveform

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Introduction to state machine

This article is designed with a "10011" sequence detector that is designed with a Moore type state machine.

Moore type state machine:The output is only determined by the current state, Ie, = f (status, input), output = f (status);
MEALY type state machine:The output is not only related to the current state, but also related to the current input value., Ie subsequent state = f (status, input), output = f (status, input);

Below is a molar state transition chart

The module design code is as follows:

`timescale 1ns/1ps
module detector_Moore(clk,rst_n,din,dout);
  input clk,rst_n,din;
  output dout;
  reg dout;
  reg [2:0] pr_state,next_state;
  parameter s0=3'b000,s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b100,s5=3'b101;

  always@(posedge clk or negedge rst_n)
    begin
      if(rst_n==1'b0) pr_state<=s0;
      else pr_state<=next_state;
    end
  
  always@(pr_state or din)
    begin
      next_state<=3'bxxx; 
      dout<=1'b0;
      case(pr_state)
      s0:                // the state is 0
         begin
           dout<=1'b0;
           if(din==1'b1) next_state<=s1;
           else next_state<=s0;
         end
      s1:               //the state is 1
         begin
           dout<=1'b0;
           if(din==1'b1) next_state<=s1;
           else next_state<=s2;
         end
      s2:               //the state is 10
         begin
           dout<=1'b0;
           if(din==1'b1) next_state<=s1;
           else next_state<=s3;
         end
         
      s3:               //the state is 100 
         begin
           dout<=1'b0;
           if(din==1'b1) next_state<=s4;
           else next_state<=s0;
         end
      s4:               //the state is 1001
         begin
           dout<=1'b0;
           if(din==1'b1) next_state<=s5;
           else next_state<=s2;
         end
      s5:               //the state is 10011
         begin
           dout<=1'b1;
           if(din==1'b1) next_state<=s1;
           else next_state<=s2;
         end
      endcase
    end
endmodule

The test platform is as follows:

`timescale 1ns/1ps
module detector_Moore_tb;
  reg clk,rst_n,din;
  wire dout;
  detector_Moore u1(.clk(clk),.rst_n(rst_n),.din(din),.dout(dout));
 /*initial begin
    `ifdef DUMP_VPD
     $vcdpluson();
    `endif
          end
  */
  always #50 clk=~clk;
  initial
    begin
      clk=1'b1;
      rst_n=1'b0;
      din=1'b1;
      #100 rst_n=1'b1; din=1'b0;
      #100 din=1'b1;
      #100 din=1'b0;
      #100 din=1'b0;
      #100 din=1'b1;
      #100 din=1'b1;
      #100 din=1'b0;
      #100 din=1'b0;
      #100 din=1'b1;
      #100 din=1'b0;
      #100 din=1'b0;
      #100 din=1'b1;
      #100 din=1'b1;
      #100 din=1'b1;
      #100 din=1'b0;
      #100 din=1'b1;
      #100 din=1'b0;
      #200 $finish;
    end

initial begin 
	$fsdbDumpfile("detector_Moore.fsdb");
	$fsdbDumpvars(0);

end
endmodule

Makefile simulation script VCS + VERDI

vcs:
	vcs -sverilog -full64 +cli+4  detector_Moore.v detector_Moore_tb.v \
	-timescale=1ns/1ps \
	-Mupdate +lint=all +notimingcheck +v2k  \
	-P ${DEBUSSY_HOME}/share/PLI/VCS/LINUX64/novas.tab \
	${DEBUSSY_HOME}/share/PLI/VCS/LINUX64/pli.a \
	+race=all \
	-R \
	-l run.log


sim: 
	./simv -R -ucli -i run.tcl -l run.log

verdi:
	#verdi -sverilog -f vcs_img_external_tb_top.sv.f +define+GLS -top img_external_tb_top &
	#verdi -sv -f filelist.f -top tb_top -ssf dut.fsdb &
	verdi -sv detector_Moore.v detector_Moore_tb.v +define+GLS -top detector_Moore_tb.v &

Run.tcl file

fsdbAutoSwitchDumpfile 1000 "detector_Moore.fsdb" 13 "fsdb.log"
fsdbDumpvars 1 detector_Moore_tb
#
#run 100ms
#run 5.0ms
run
exit

Simulation waveform