PCI9054

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This article introduces the recent use of CPCI, the Internet has collected a bit of PCI data, CPCI is a subset of PCI, the bridge chip used is divided into two main types, so I won't go into details here. As for PCI, I will introduce the following as follows:

With the rapid development of Windows graphical user interface and the wide application of multimedia technology, the system requires high-speed graphics processing and I/O throughput, which makes the original ISA and EISA bus far from adapting and becomes the main bottleneck of the whole system. . To this end, in the second half of 1991, Intel first proposed the PCI concept, and together with more than 100 companies such as IBM, Compaq, AST, HP Apple, NCR, DEC, etc., colluded with the development of computer bus, and established the PCI Group.

PCI：Peripheral Component Interconnect，Peripheral interconnect busIt is a local bus and has become a new standard for local buses. It is widely used in current high-end microcomputers, workstations, and portable microcomputers. Mainly used to connect display cards, network cards, sound cards.PCIBus is32Bit synchronous multiplexing bus. Its address and data line pins areAD31～AD0。PCIWorking frequency is33MHz。

A PCI bus feature

1.PCI bus features
　　(1) High transmission rate The maximum data transfer rate is 132MB/s. When the data width is upgraded to 64 bits, the data transfer rate can reach 264MB/s. This is unmatched by other buses. It greatly alleviates the data I / O bottleneck, so that the functions of high-performance CPU can be fully utilized to meet the needs of high-speed device data transmission.
　　(2) Multi-bus coexistence The PCI bus allows multiple buses to coexist in one system and accommodate devices of different speeds to work together. The CPU bus and the PCI bus are bridged by the HOST-PCI bridge component chip; the PCI bus and the ISA/EISA bus are bridged by the PCI-ISA/EISA bridge component chip to form a hierarchical multi-bus system. The high-speed device is removed from the ISA/EISA bus and moved to the PCI bus. The low-speed device can still be hung on the ISA/EISA bus, inheriting the original resources and expanding the system compatibility.
　　(3) Independent of the CPU The PCI bus is not attached to a specific processor, that is, the PCI bus supports multiple processors and new processors to be developed in the future. When changing the processor type, the corresponding bridge components can be replaced.
　　(4) Automatic identification and configuration of peripherals User is easy to use.
　　(5) Parallel operation capability。
2. The main performance of the PCI bus
(1) The bus clock frequency is 33.3MHz/66.6MHz.
(2) Bus width 32 bits / 64 bits.
(3) The maximum data transmission rate is 132MB/s (264MB/s).
(4) Support for 64-bit addressing.
(5) Adapt to 5V and 3.3V power supply environment.

Two PCI bus signals

The signal lines defined by the PCI bus standard are usually divided into two major categories, required and optional. The total number of signal lines is 120 (including power, ground, reserved pins, etc.). Among them, the necessary signal lines: 49 main control devices and 47 target devices. Optional signal lines: 51 (mainly for 64-bit extensions, interrupt requests, cache support, etc.).
The master device refers to the device that has obtained the control of the bus, and the device that is selected by the master device for data exchange is called the slave device or the target device. As the master device, 49 signal lines are required. If it is a target device, 47 signal lines are required, and there are 51 optional signal lines. With these signal lines, data and addresses can be transmitted to implement interface control, arbitration, and system functions. PCI local bus signal such asThe following figureShown. The following is a description by function grouping.


System signal
　　CLK IN：System clock signalProvides timing for all PCI transfers and is an input signal for all PCI devices. The frequency can be up to 33MHz/66MHz, which is also called the operating frequency of PCI.
　　RST# IN：Reset signal.Used to force all PCI-specific registers, sequencers, and signals to their initial state.
2. Address and data signals
　　AD[31：：00]T/S：Address, data multiplexed signal. The transfer of addresses and data on the PCI bus must be performed during the FRAME# valid period. When the first clock is valid when FRAME# is active, the signal on AD[31::00] is the address signal, which is called the address period; when IRDY# and TRDY# are both active, the signal on AD[31::00] is The data signal is called the data period. A PCI bus transfer cycle consists of an address period followed by one or more data periods.
　　C/BE[3：：0]# T/S：Bus commands and bytes allow multiplexing of signals. In the address period, these four lines transmit time bus commands; during the data period, they transmit the time byte enable signal, which is used to specify 4 data bytes on the AD[31::00] line during the data period. Which bytes are valid data for transmission.
　　PAR T/S：Parity signal. It performs parity check by AD[31::00] and C/BE[3::0]. The master drives PAR for address cycles and write data cycles, and the slave drives PAR for read data cycles.
3. Interface control signal
　　FRAME# S/T/S：Frame period signal, driven by the master device. Represents the start and duration of a bus transfer. When FRAME# is valid, it indicates the start of bus transmission; during its valid period, the address is transmitted first, and then the data is transmitted; when FRAME# is revoked, the bus transmission is predicted to end, and the data transmission of the last data period is performed when IRDY# is valid. .
　　IRDY# S/T/S：Master device ready signal. IRDY# should be used in conjunction with TRDY#. When both are valid, the data can be transmitted. Otherwise, it is not ready for two to enter the waiting period. During the write cycle, when the signal is valid, it indicates that the data has been submitted by the master device to the AD[31::00] line; during the read cycle, when the signal is valid, it indicates that the master device is ready to receive data.
　　TRDY# S/T/S：Ready signal from device (selected device). Similarly, TRDY# should be used in conjunction with IRDY#. Only when both are valid, data can be transmitted.
　　STOP# S/T/S：The slave device requires the master device to stop the signal of the current data transmission.. Obviously, this signal should be sent by the slave device.
　　LOCK# S/T/S：Lock signal. The exclusive use of the lock signal LOCK# for exclusive access to a device that may require multiple bus transfer cycles to complete. For example, if a device has its own memory, it must be able to lock in order to achieve full exclusive access to the memory. That is, the operation of this device is exclusive.
　　IDSEL IN：Initialize the device selection signal. Used as a chip select signal during parameter configuration read/write transfers.
　　DEVSEL# S/T/S：Device selection signal. This signal is issued by the slave when it recognizes the address. When it is valid, it indicates that a certain device on the bus has been selected and is the slave that is currently accessed.
4. Arbitration signal (only for bus master)
　　REQ# T/S：Bus occupancy request signal. This signal effectively indicates that the device that is driving it requires the use of a bus. It is a point-to-point signal line and any master device has its own REQ# signal.
　　GNT# T/S：Bus occupancy enable signal. This signal is valid, indicating that the request to apply for the device occupying the bus has been obtained.
5. Error report signal
　　PERR# S/T/S：Data parity error report signal. A device can report a PERR# only after responding to the device selection signal (DEVSEL#) and completing the data period.
　　SERR# O/D：System error reporting signal. Used as reporting address parity errors, data parity errors in special command sequences, and other system errors that can cause catastrophic consequences. It can be sent by any device.
6. Interrupt signal In the PCI bus, interrupts are optional and do not have to be.
　　INTA# O/D：Used to request an interrupt.
　　INTB# O/D、INTC# O/D、INTD# O/D：Used to request an interrupt, only meaningful for multifunction devices. The so-called multi-function device refers to the concentration of several independent functions in one device. The connection between each function and the interrupt line is arbitrary without any additional restrictions.
7. Other optional signals
(1) Cache support signals: SBO# IN/OUT, SDONE IN/OUT
(2) 64-bit bus extension signal: REQ64# S/T/S, ACK65# S/T/S、AD[63：：32]T/S、C/BE[7：：4]#T/S、PAR64 T/S。
(3) Test access port/boundary scan signals: TCK IN, TDI IN, TDO OUT, TMS IN, TRST# IN.

9054 feature description

 
The PLX9054 acts as an interface chip that transfers information between the PCI bus and the local bus. PCI card is to use this feature of plx9054, through the interface control circuit, for the periphery deviceAnd build a hardware bridge between PCs and complete dataSmooth transmission. The following describes a specific implementation method.
4.1 interface chip jobsMode selection
4.1.1 Local Bus jobsthe way
Choose Plx9054 local bus can jobsIn M, C, J three modes.
M mode is specifically for motora company mcu designof jobsmode. This model specifically provides a direct, non-multiplexed interface for Motorola's mpc850 and mpc860.
C mode is a kind of similar to single chip microcomputer jobsthe way . In this kind of jobsIn the mode, the 9054 chip passes the inter-chip logic control, and the pci address line and dataLine separate, very convenient for local jobsTiming provides a variety of high difficulty jobsMode, generally more widely used in the system designin. For this jobsthe way , designAs long as the timing control is strictly controlled, the timing process of various timing control lines at the local end and the pci end is strictly controlled, and the 9054 chip can be well applied.
J mode is a type without a local master jobsMode, its benefit is the address dataThe lines are not separated, strictly emulating the timing of the pci bus. Just for the timing control, a lot of control signals are added, so designLearn about pci protocolAnd better control pci CommunicationProvides better space.
This topic selects the c mode of plx9054 jobsthe way . Plx9054 jobsThe mode can be selected using the mode selection pin. For the plx9054 chip in the 176pin-PQFP package. The mode selection pin is pin156 (mode1), pin157 (mode0), and the combination mode is as shown in Figure 4-1/ according to the above combination, in this circuit. designIn the middle, pull the mode0 and mode1 pins low to ensure that mode[0:1]=00. Figure 4-1 Local bus jobsMode selection
 
4.1.2 data data transmissionMode selection
9054 supports main mode, slave mode, dma transmissionThe mode can be used for trial cards and embedded systems, which are briefly introduced below.
Pci initiator operation
The main mode operation is to allow the local CPU to access the memory and I/O interface of the PCI bus. Mode selection must be enabled in the pci command register. Like pci master deviceMemory and i/o range registers, pci base register, main deviceConfiguration and command registers, etc. Main mode operation includes pci master deviceMemory and i/o decoding, pci master deviceMemory and i/o configuration access, pci dual address cycle access, pci master deviceMemory writes and invalid operations.
From device（pci target）
Slave mode is to allow mastering on the pci bus deviceAccess to the configuration registers and memory of the plx9054 on the local bus, supporting burst and single-cycle modes transmission. Plx9054 is passed from a 16-word pci deviceFIFO and 32 words long pci from deviceWrite FIFOs to support burst and single-cycle memory mapped access and i/o mapped access from the PCI bus to the local bus. The Pci base register is used to set the pci memory and i/o address space. Slave mode operations include delayed read operations, read ahead operations, and so on. This mode has non-multiplexed addresses and dataBus, circuit designTiming and control are relatively simple.
(direct memory access) operation
The Plx9054 has a powerful dual-channel scatter/gather DMA controller that supports efficient bursts of pci host and adapter memory transmission. Two independent dma channels can be used from local bus to pci bus and from pci bus to local bus transmission data. Each channel includes a dma controller and a dedicated bidirectional FIFO. Both channels support blocks transmission, dispersion/collection transmission, application or not using EOT transmissionWait. Mode selection becomes a pci bus master in plx9054 deviceBefore by the Lord deviceThe enable bit (pcicr[2]) is enabled. In addition, both DMA channels can be programmed to implement 8, 16, 32bit local bus bandwidth, enabling/disabling internal wait cycles, enabling/disabling local bus bursts. transmission; execute pci memory write and invalid operation; set pci interrupt (inta) or see if local interrupt (i.int), etc. data transmissionThe choice of mode is mainly based on the hardware maker's hardware designDepending on the needs. When the hardware producer chooses to have pci to initiate control, then 9054 should be pci jobsGoal, this time you should choose the pci target method of 9054. When the hardware producer chooses to initiate control from the local end, the 9054 becomes the master. deviceAnd pci becomes 9054 jobsGoal, this situation should choose the pci master mode of Po 4 . And in dataDma transmissionAt the time, 9054 is the master of the pci end and the local end. device, it has a dma controller, it can completely control the dma from the PC. At this time, 9054 jobsIn dma transmissionthe way. This topic is initiated by the PC to control the request to read and write to the external sram data, so choose plx9054 slave mode (pci target) transmissionthe way. In this mode, plx9054 is the target for the pci end deviceOn the local side is the master device，
Let's take the pci target as an example to give the number of plx9054 in slave mode. transmissionFigure, Figure 4-2 Figure 4-2 pci target read in this transmissionIn the mode, 9054 is used as the local bus master deviceLocal bus arbitration via lhold# and lhokda#.
The arbitration process is briefly described below. When plx9054 receives the read/write control command issued by the pci terminal, it sends an lhold control signal to the local end, indicating that the pci end is ready to be completed, and then sends the lholda signal to the 9054, indicating that both parties are ready for normal operation and operation. One-step function implementation. Otherwise, wait for 12 clock cycles to release the bus. The specific arbitration timing is as follows.
Figure 4-3 Local Bus Arbitration 4-2 Interface Circuit designAnd the realization of the 4-2-1 circuit hardware structure diagram Plx9054 as a bridge chip, provides three interfaces of pci bus, eeprom, local bus, hardware circuit block diagram shown in Figure 4-4. The circuit is divided into three parts.
The interface circuits of each part are respectively introduced below.
4-2-1-1plx9054 and pci bus interface 1 connection signal describes the first part of the hardware interface circuit when the connection signal line between the 9054 and the pci slot. These signals include addresses dataTaking the signal c/be[3:0] and pci protocolControl signals PAR, .FRAME#, TRDY#, STOP#, IDSEL, DEVSEL#, etc. In the circuit connection, the signal lines corresponding to each other are connected together.
Figure 4-4 Hardware circuit structure diagram In the judgment bus signal, except for RST#, INTA#~INTD#, all other signals are sampled on the rising edge of the clock. Each signal has a setup and hold time relative to the clock front. During this time, no signal jitter is allowed. Once the event is over, the signal changes are irrelevant. This setup and hold time is different for different signals. For lock#, irdy#, trdy#, frame#, devsel#, stop#. Req#, gnt# and perr# These signals have setup and hold times on each clock front. For c/be[3:0]# at transmissionWhen the bus command is used, the relationship between the follow and the hold time on the clock edge is required when the frame# is first established. If transmissionThe byte enable signal is to be completed during an address period or dataEach clock edge after the period guarantees a corresponding setup and hold time.
 
4.2.1.2 Interface between PLX9054 and EEPROM
1. EEPROM selection
       PLX54 recommendThe serial EEPROM can be used with a 5V powered serial EEPROM as follows:
(1) FM93CS46L from Fairchild Semicondctor;
(2) Holtel's HT93 LC46 (put the ORG pin high to set it to 16 bits)
(3) IS93C46 of Integrated Silicon Solution;
(4) Microchip Technology's 93C46B, 83LC46B or 93AA46 (put the ORG pin high to set to 16 bits)
(5) Rohm's BR93LC46;
(6) Seiko's S-93C46A
(7) ST Microeletronic's M93C46 or M93S46 or other compatible serial EEPROM.
This project selected Microchip Technology's serial EEPROM-96LC66B as the configuration memory for the PLX9054.
The 96LC66B is a 4K low voltage serial EEPROM that is used to form a 256 x 16 bit memory block. The 93LC66B features a 3-wire pass-through interface bus and is compatible with Microwire industry standards. The lowest single power supply for this device jobsVoltage up to 2.5V, commercial/industrial temperature range (-40C to +85C) with advanced CMOS technology. These make the 93LC66B an ideal device for low-power, non-volatile memory applications. The 93LC66B is available in an 8-pin PDIP package and a surface-on-the-shelf SOIC package.
 
2. EEPROM interface
The PLX9054 has four signal lines for interfacing with EEPROM: EESK.EEDO.EEDI. and EECS, as shown in Table 4-1. The serial EEPROM also has four corresponding pins: CS.DI/DO.CLK. The details are as follows:
      （1）CS     
CS is the chip select line of serial EEPROM
      （2）DI/DO         
DI and DO are connected together with EEDI and EEDO, and connected to a pull-up group. After resetting. PCI9054 will try to read from Serial EEPROM data. The first double word will be used to identify if the Serial EEPROM has been programmed. If it is all "1", it means empty Serial EEPROM: If all is "0", it means there is no Serial EEPROM. In both cases, the PCI9054 will use the default value. After the system is up, use the PLXMON to program the Serial EEPROM.
      （3）CLK        
The 3.3V serial EEPROM clock is derived from the internal clock of the PCI bus. The PCI9054 generates a serial EEPROM clock by internally dividing the PCI clock by 32. The circuit connection diagram of PLX9054 and EEPROM is shown in Figure 4-7.
4.2.1.3 Interface between PLX9054 and LOCAL BUS
1. Connection signal description
The third part of the hardware circuit is the 9054 and the Local end. Some of the pin signals used in the Local end of the PLX9054 chip are described as follows:
LHPLD: Apply to use the local bus, output signal;
LHOLDA: replies to LHOLD, input signal;
ADS: The start of the new bus access effective address, when the bus accesses the first clock setting, the output signal;
BLAST: represents the last transfer of the bus access, the output signal;
LW/R: high level indicates a read operation, and the level indicates a write operation and an output signal;
LA: Address line.
      LD： dataline.
READY: indicates reading on the bus dataValid or write datacarry out. Used to connect the PLX9054 wait state generator to input signals.
 
2. On the LOCAL bus data transmission   
At the beginning of PCITarget single-cycle write, PLX9054 first drives LHOLD to apply for Local bus. If Local bus is idle, control module drives LHOLDA to effectively transfer bus control to 9054. Then, PLX9054 will drive ADS# (address latch signal), LW/ R# (read-write signal), LBE# (byte enable signal) and LA (address signal), the control module will latch and decode the above signals to determine the target and operation type. The timing of the local write operation is shown in Figure 4-8. On the LOCAL side, the memory selected by this interface card is MOTOROLA's MCM6706B (32×8bit), and the storage period is 8 ns. Since the static DATA line and the ADDR line are directly connected to the DAA and ADDR lines of MOTOROLA's SRAM. In addition, the LRW/R line of the 9054 is divided into two: one passes through the NOT gate and becomes a negative signal; the other remains unchanged, and is connected to the WR connection of the SRAM and the RD of the SRAM, respectively.
 
4.2.2 Register Configuration
      designGood interface circuit, hardware design jobsIt’s only half done. Since the PLX9054 is a general-purpose PCI interface function chip, its function does not necessarily meet the needs of users, so further functional register configuration is required, so that the interface circuit has a specific function.
The configuration of the registers includes the configuration of the EEPROM initialization, the LOCAL function register, and the PCI configuration registers. The following are introduced separately.
 
4.2.2.1 EEPROM Initialization
The configuration of the PLX9054 requires 68 bytes of configuration information, including the following information: deviceThe identification number, the supplier code number, the size of the three spaces of the Local bus, and the base addresses of the three spaces. The information to be configured can be written to the register in advance using the programmer, or the EEPROM can be configured under plxmon in plxsdk. In this way, the system resources we apply will be configured when the computer is started. The specific configuration process is as follows:
1. EEPROM initialization
During the power-on self-test of the computer, the RST# signal of the PCI bus is reset and the default value of the PLX9054 internal register is responded. The PLX9054 outputs the local LRESET# signal and detects the serial EEPROM.
If the first 33 bits in the serial EEPROM are not all 1, then the PLX9054 determines that the serial EEPROM is not empty. The user can load the contents of the EEPROM into the internal registers of the PLX9054 by writing a 1 to the 29 bits of the odd CNTRL of the 9054.
If serial dataStarting with 1, it indicates that the serial EEPROM does not exist. For the absence of a serial EEPROM, the EEDO pin needs to be pulled low to prevent false detection of the low start bit, while pl9054 stops the serial eeprom loading and transitions to the default value: when the serial eeprom valid bit CNTRL [28] =1, real or random will be read in the serial eeprom data. I have had a lot of trouble here and I can't get into the system. After finding the cause, I found that the EEPROM could not be fed into the system after it was soldered. After many attempts, it was solved.
2. Read and write eeprom read and write serial
The steps of eeprom are as follows:
(1) Enable serial eeprom chip select signal by writing 1 to 25 bits of cntrl eecs
(2) Write 24 to cntrl, then write 0 to generate the serial eeprom clock, on the rising edge of the clock. dataRead and write
(3) Write command code to eeprom
(4) If the serial eeprom exists, the command code is returned after returning 0 as the start bit.
(5) reading and writing data
(6) Write 0 to the mixed register cntrl[25] to end the access to the eeprom, at which point eecs is low;
3. EEPROM serial dataLoading
The PLX9054 chip loads the information in the EEPROM, first loading the upper 16 bits [31:16], and starting from the high significant bit 31, then loading the lower 16 bits, starting at 15 bits. Therefore, the loading order is the device ID number, the manufacturer ID number, and the like. In the table dataThe value can be programmed by the EEPROM burner. The mixed register CNTRL allows one bit of the EEPROM to be programmed at each time. Partially loaded dataAs shown in Table 4-2.
The values ​​in the serial EEPROM can also be configured via PLXmon in PLXSdk.
Figure 4-9 shows the configuration window of the EEPROM under the PLxmon interface.
 
4.2.2.2 PLX9054 Register Configuration
The PLX9054 configuration register is configured according to the specific hardware. deviceConfigure it. Whether its configuration is correct or not is hardware deviceCan it be normal? jobsKey and related to hardware deviceCan fully play its performance, it can be said that its configuration register configuration is using PC9054 chip for hardware designThe key to success.
1. PCI configuration register configuration
Configuring the PCI configuration register is relatively simple. Mainly fill in the manufacturer ID number, device ID number, class code subsystem ID number and subsystem manufacturer ID number. For PCI9054, the manufacturer ID number is 10B5, the device ID number is 9054, the subsystem number is 9054, the subsystem ID number is 10B5, and the class code number is 0680, indicating that it is a bridge. deviceOther bridges in deviceclass.
2. Local configuration register configuration
The configuration of the local configuration register is actually the configuration of the local address space and its local bus attributes. These configurations are configured according to the hardware resources of the actual developed hardware boards. For example if designThe interface card uses only one local address space, and only needs to apply for the corresponding PCI address space to the computer for this address space. PCI9054 is essentially a bridge deviceIt converts the various operations of the PCI bus to a certain PCI bus address space, including reading, writing, etc., into operations on the corresponding address bus. therefore deviceThe task of the staff configuration register is to map a certain local address to a PCI address. In other words, when the host CPU wants to access the local address space, it must know its corresponding PCI bus address.
The following describes the process of mapping the local address bus to the PCI bus by taking the local address space 0 as an example.
First set the range of local address space 0. The value of this register reflects whether the address space is mapped to the PCI memory address space or the I/O address space, and the size of the address space. Initialize the PLX9054 chip to read the value from the EEPROM and place it in the PCI configuration register address. When the host writes FFFFFFFFH to it and then reads back its value, the place where it is 1 indicates the assigned address to be allocated. For example, when the content of the local address range register is FFF00000H, the PCI base address allocated to the address space 3 by the PCI bus may be 12300000H, which is random at this time. The size of the memory area in this example is 1M.
Next, the remapping register of the local address space 0 is set, that is, the local bus address corresponding to the address 12300000H is filled. For example, it can be filled with 04000001H to indicate that its local base address is 04000000H. That is, access to the PCI address 12300000H on the PCI bus is access to the 04000000H unit.
 
4.3 PCB board electrical requirements
        designIn high-speed analog and digital hybrid circuits, it is necessary to fully consider the chip delay of the digital IC to ensure the accuracy of the timing, and to make the interference problem of digital and analog signals in the north. Wiring of high-frequency signal lines, IC power supply decoupling, ground plane design, amplifier noise suppression, etc., in order to guarantee designRate and accuracy requirements.
PCI bus electrical specificationDefines the electrical performance and constraints of all PCI components, system expansion boards, and pin assignments for expansion board connectors. Thus in the circuit designAll the leads on PCI must meet PCI electrical specification。   
The following is a brief introduction to some of the electrical requirements that need to be noted during the PCB manufacturing process.
1. Decoupling
PLX9054 uses CMOS technologyIt has a good suppression of noise, but the noise caused by some high-speed signals (such as PCI clock signal) must be considered. A 0.1uf capacitor should be used as the decoupling capacitor. The decoupling capacitor is as close as possible to the power supply and ground.
2, routing requirements
(1) 32-bit from the edge of the PCI slot to the PLX9054 dataThe maximum trace length of the bus must not exceed 1500 mils.
(2) The clock signal trace length from the edge of the PCI slot to the PLX9054 must be 2500 mils (+/- 100 mils). The lead wire can only be routed on one side of the PCB and curved at the corner. Avoid using a right angle. You can use the "snake" shape to meet the length requirements.
3, power consumption
All PCI connectors require four power lines: +5V, +3.3V, +12V, -12V. 3.3V is provided by the expansion board that requires this voltage, and +5V and +_12V are provided by the system. The PCI board allows a maximum power of 25W and can be obtained from all four power lines provided by the connector. In the worst case, all 25W of power can only be obtained from the +5V and +3V lines of the PCI slot. In addition, it should be noted that the control signals of PCI basically require pull-up resistors, in order to ensure that they are not deviceThe drive bus still has a stable value. Such signals are: FRMAE#, TRDY#, IRDY#, DEVSEL#, STOP#, SERR#, etc. In addition, the interface circuit PCB board designThere are still many electrical requirements, which are not repeated here.

9054Introduction:

The main function of PCI9054 is to realize data communication between PCI bus and local bus (generally Harvard structure). There are three kinds of data transmission modes: main mode, slave mode and DMA mode.

The PCI9054 chip is mainly composed of two data FIFO channels, internal registers, EEPROM and control circuits. The two channels are DMA0 and DMA1 respectively, and their functions are basically the same, and DMA0 can also transmit command commands.

PCI9054 has three working modes: M, J, C

M mode, a non-multiplexed interface directly prepared for Motorola's MPC850 and MPC860;

C mode, address, data lines are not multiplexed;

J mode, address data line multiplexing.

Due to MThe mode is relatively small, JMode control is more complicated, generally use Cmode.

PIN definition:

All modes

AD[31:0] (Address and Data) address and clock multiplexing, first of all an address segment, followed by one or more data segments, support burst mode read and write;

The C/BE[3:0]# (Bus Command and Byte Enables) bus command and data enable multiplexing pins are used as bus commands when AD is the address line and as data when AD is the data line.

When DEVSEL# (Device Select) is valid, it indicates that the current device is selected as the input port;

FRAME# (Cyclone Frame) is driven by the master device to indicate that the current device has started to access and the bus starts transmitting data. Valid: Transfer data. Invalid: complete the transmission of the last data;

GNT#(Grant) is used to indicate that the currently accessed device has been accepted.

IDSL (Initialization Device Select) is used as a chip select signal when the configuration register is read or written;

INTA# (Interrupt A) PCI interrupt request;

IRDY# (Initiator Ready) indicates that the current data is valid and can be completed and completed.

LOCK#(Lock) prompts for automatic operation and requires several clocks to complete the operation;

PAR (Parity) is the base parity of the AD and C/BE two-part bus. When the address is transmitted, the PAR is stable for one clock cycle after the address is transmitted. For data segments, PAR is stable for one clock cycle after IRDY# or TRDY# is active. Once the PAR data is valid, it will remain valid until the end of the current data or address segment transmission;

PCLK (Clock) system clock, 9054 works at 33MHz;

PERR# (Parity Error) is used to report parity errors, excluding special periods;

PME# (Power Management Event) wakeup interrupt;

REQ# (Request) request signal to inform the bus decider that the current device must use the bus;

RST# (Reset) system reset;

SERR# (System Error) is used to report parity errors and other system errors for special periods;

STOP#(Stop) requires the main system to stop the data transmission of the current device;

TRAY# (Target Ready) target device is ready to transfer current data;

BIGEND#（Big Endian Select）

CCS# (Configuration Register Select) low effective chip select signal;

EECS (Serial EEPROM Chip Select) selects the serial EEPROM;

EEDI/DDEO (Serial EEPROM Data In/ Serial EEPROM Data Out) controls serial EEPROM read and write data;

EESK (Serial Data Clock) EEPROM read and write clock;

ENUM# (Enumeration) burst output, used to indicate that an adapter using the PCI9054 chip has just been added or removed from a CPI bus channel;

Local clock input of LCLK (Local Processor Clock);

LEDon/LEDin LED control;

LFRAME# (PCI Buffered FRAME# Signal) indicates the status of the PCI bus;

LINT# (Local Interrupt) Local bus interrupt. Input to 9054, active low, triggering a PCI interrupt. As an output, wait until a trigger occurs;

LRESETo# (Local Bus Reset Out) When the PCI9054 chip is reset, this pin can be used to drive the RESET# signal of other chips;

MDREQ#/MDPAF/EOT#

MODE[1:0] (Bus Mode) 11: M mode; 10: J mode; 01: Reserved; 00: C mode;

TEST (Test Pin) chip detects the pin, the high is the detection, the low is the work, and the low is usually low;

USERi/BACK0#/LLOCKi# Multiplexed Pins

USERo/DREQ0#/LLOCKo# Multiplexed Pins

VDD power supply

VSS ground

C mode:

ADS# (Address Strobe) indicates that the address is valid and the bus has new equipment access;

BLAST# (Burst Last) This signal is controlled by the local bus and represents the transmission of the last character;

BREQi (Bus Request In) local bus control, data is input from the local bus;

BREQo (Bus Request Out) PCI bus control, data is output from the PCI bus;

BTERM# (Burst Terminate) is used as an input to indicate the end of the current burst operation, to start reading and writing the next burst address, and to be used with the programmable wait state generator inside the PCI9054. As an output, used with READY# to interrupt the current burst operation and start the next burst operation address cycle;

DP[3:0] (Data Parity) parity data;

LA[31:2] (Address Bus) address bus;

LBE[3:0]# (Byte Enable) control data is valid, different modes have different control methods;

LD[31:0] (Data Bus) data bus;

The LHOLD (Hold Request) transmission requires the use of a local bus. After the local bus decides to allocate to the current device, the decider sends LHOLDA signal feedback.

LHOLDA (Hold Request) feedback signal;

LSERR# (System Error Interrupt Output) system error interrupt;

LW/R# (Write/?Read) low level read, high level write;

READY#(Ready Input/Output) means that the data is ready and valid regardless of the master or slave mode;

WAIT# (Wait Input/Output) is used as an input to control the PCI9054 insertion wait state. As an output, the PCI9054 is in the Ready state.

J mode:

ADS# (Address Strobe) indicates that the address is valid and the bus has new equipment access;

ALE (Address Latch Enable) address is valid when transmitting, and invalid when data is transmitted;

BLAST# (Burst Last) This signal is controlled by the local bus and represents the transmission of the last character;

BREQi (Bus Request In) local bus control, data is input from the local bus;

BREQo (Bus Request Out) PCI bus control, data is output from the PCI bus;

BTERM# (Burst Terminate) is used as an input to indicate the end of the current burst operation, to start reading and writing the next burst address, and to be used with the programmable wait state generator inside the PCI9054. As an output, used with READY# to interrupt the current burst operation and start the next burst operation address cycle;

DEN# (Data Enable) is used in conjunction with DT/R# to control the data transceiver connected to the local bus;

DP[3:0] (Data Parity) parity data;

DT/R# (Data Transmit/Receive) is used in conjunction with DEN#. When valid, PCI9054 receives data.

LA[28:2] (Local Address Bus) local bus address;

LAD[31:0] (Address/Data Bus) Address Period: This bus contains the upper 30 bits of the physical address bus. Data cycle: the bus transmits 32-bit data;

LBE[3:0]# (Byte Enable) control data is valid, different modes have different control methods;

The LHOLD (Hold Request) transmission requires the use of a local bus. After the local bus decides to allocate to the current device, the decider sends LHOLDA signal feedback.

LHOLDA (Hold Request) feedback signal;

LSERR# (System Error Interrupt Output) system error interrupt;

LW/R# (Write/Read) low level read, high level write;

READY#(Ready Input/Output) means that the data is ready and valid regardless of the master or slave mode;

WAIT# (Wait Input/Output) is used as an input to control the PCI9054 insertion wait state. As an output, the PCI9054 is in the Ready state.
           

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