The design of the asynchronous FIFO

Async_fifo classic framework:

The address of the empty judgment is converted by Gray code, and the output is shot
The high two bit is the opposite, and the other bit is the same: the same:
Both are equal to empty;
The extension of RAM is as follows:

dual_ports_sram:

module dual_port_ram #(parameter WIDTH= 8,parameter DEPTH = 16,parameter ADDR=$clog2(DEPTH))
    (input wclk,
    input rclk,
    input [WIDTH-1:0]wdata,
    input wenc,
    input renc,
    input [ADDR-1:0]waddr,
    input [ADDR-1:0]raddr, 
    output reg [WIDTH-1:0]rdata
);
/*----------sram----------*/
reg [WIDTH-1:0]ram[DEPTH-1:0] ;

/*------write operation -------*/
always @(posedge wclk) begin
    if(wenc)
        ram[waddr] <= wdata;
end

/*------read operation -------*/
always @(posedge rclk ) begin
    if(renc)
        rdata <= ram[raddr];
end

endmodule //dual_port_ram

async_fifo.v

//async_fifo
`timescale 1ns/1ps

module async_fifo #(parameter WIDTH=8,parameter DEPTH=16,parameter ADDR_BIT = $clog2(DEPTH);)(
    input rrstn,wrstn,
    input wclk,rclk,
    input wenc,renc,
    input [WIDTH-1:0]wdata,
    output wire [WIDTH-1:0]rdata,  //
    output wire full,
    output wire empty
);

/*---------address declare-------------*/

reg [ADDR_BIT:0]waddr;
reg [ADDR_BIT:0]raddr;

/*------------write addr---------------*/
always@(posedge wclk or negedge wrstn)begin
    if(!wrstn)
        waddr <= 'b0;
    else if(wenc && ~full)
        waddr <= waddr + 1'b1;
    else
        waddr <= waddr;
end

/*------------read addr---------------*/
always@(posedge rclk or negedge rrstn)begin
    if(!rrstn)
        raddr <= 'b0;
    else if(renc && ~empty)
        raddr <= raddr +1'b1;
    else
        raddr <= raddr;
end

/*------------W2R bin to gray---------------*/
wire [WIDTH:0]r_gaddr ;  
wire [WIDTH:0]w_gaddr ;

assign r_gaddr = raddr ^ (raddr>>1);  //bin to gray code;for
assign w_gaddr = waddr ^ (waddr>>1);

reg [ADDR_BIT:0]w_gaddr_reg;  //Hit one beat in the write clock domain
always@(posedge wclk or negedge wrstn)begin
    if(!wrstn)
        w_gaddr_reg <= 'd0;
    else
        w_gaddr_reg <= w_gaddr;
end

reg [ADDR_BIT:0]r_gaddr_reg;//Hit one beat in the read clock domain
always @(posedge rclk or negedge rrstn) begin
    if(!rrstn)
        r_gaddr_reg <= 'd0;
    else
        r_gaddr_reg <= r_gaddr;
end

/*------------After Clock Domain Crossings, hit two beats to make empty judgment----------------*/
reg [ADDR_BIT:0]addr_w2r_t;
reg [ADDR_BIT:0]addr_w2r;
always@(posedge rclk or negedge rrstn)begin
    if(!rrstn)begin
        addr_w2r_t <= 'd0;
        addr_w2r   <= 'd0;
        end
    else begin
        addr_w2r_t <= w_gaddr_reg;  //Send the address generated by the write clock domain into the read clock domain
        addr_w2r   <= addr_r2w_t;
    end
end

/*------------After Clock Domain Crossings, hit two beats to make full judgment---------------*/
reg [ADDR_BIT:0]addr_r2w_t;
reg [ADDR_BIT:0]addr_r2w;
always@(posedge wclk or negedge wrstn)begin
    if(!wrstn)begin
        addr_r2w_t <= 'd0;
        addr_r2w   <= 'd0;
        end
    else begin
        addr_r2w_t <= r_gaddr_reg;  //
        addr_r2w   <= addr_r2w_t;
    end
end

assign empty = (addr_r2w == addr_w2r);
assign full  = (addr_r2w == {~addr_w2r[ADDR_BIT:ADDR_BIT-1],addr_w2r[ADDR_BIT-2:0]});

/*------------sram instanse---------------*/
dual_port_ram #(.DEPTH(DEPTH),
                .WIDTH(WIDTH),
                .ADDR(ADDR_BIT))
dual_port_ram_ins(
        .wclk(wclk),
        .rclk(rclk),
        .wenc(wenc && ~full),
        .renc(renc && ~empty),
        .wdata(wdata),
        .rdata(rdata),
        .waddr(waddr[ADDR_BIT-1:0]),  //-1,,SRAM
        .raddr(raddr[ADDR_BIT-1:0])
);


endmodule //async_fifo

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