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1, synchronous reset

Advantages and disadvantages of synchronous reset:

2, asynchronous reset

Advantages and disadvantages of asynchronous reset:

3, asynchronous reset synchronous release

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1, synchronous reset

Synchronous reset, that is, if the reset signal is valid, it can only reset the circuit on the clock rising edge.

    always @ (posedge clk) begin
        if (!rst_n)
            xxxx;
    end

Notice:In this always block, the sensitive amount is only one, that is, the rising edge of CLK, this meaning, only the Always block can be executed only in the rising edge of the CLK, otherwise it will not be executed. So if the reset signal is valid, it can only wait until the CLK rising edge can execute the ALWAYS block to reset the circuit!

Advantages and disadvantages of synchronous reset:

2, asynchronous reset

The reset signal is not controlled by the clock, regardless of whether the clock edge is coming, the system will reset the system as long as the reset signal is valid.

Generally, the reset signal is highly valid.

always @ （posedge clk or negedge rst_n） 
    begin
        if (!rst_n)
            xxxx;
        else if (xx) 
            begin
                xxxx;
            end
    end

Notice:In this Always block, the sensitive amount is two, one is a posedge CLK, one is the falling edge of the reset signal RST_N (Negedge RST_N), and when the reset signal falls, what is the state of CLK, Execute the always block, ie, reset!

Advantages and disadvantages of asynchronous reset:

3, asynchronous reset synchronous release

Suppose the reset signal is effectiverst_nWhen the reset signal is invalid, it is the release of the reset signal when the reset signal is pulled.

Since the asynchronous reset signal is unable to contact the clock, both are independent, so the release of the reset signal will have a certain probability that the circuit is metastable.

The so-called asynchronous reset synchronization is released at the RST_N signal, and the RST_N signal is released immediately, and in order to prevent the appearance of the aginet state, the RST_n signal is extended by the RST_n signal to reach a period of one cycle, reaching the clock. The purpose of the CLK edge synchronization.

The classic asynchronous reset synchronous release code is as follows:

module asyn_reset(
	clk	    ,
	rst_n	,
	
	rst_s2
);

input clk	;
input rst_n	;

output reg rst_s2;

reg rst_s1;

always @ (posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		rst_s1 <= 1'b0;
		rst_s2 <= 1'b0;
	end
	else begin
	   rst_s1 <= 1'b1	;
	   rst_s2 <= rst_s1	;
	end
end

endmodule

The integrated circuit is as follows:

 

Reset signal is high, it is equivalent torst_nSampling high level;

Due to asynchronous reset needsClock rising edge is releasedTherefore, sorst_n=1After you let the signalrst_s1Level1Sampling, then play a shot of the registerrst_s2. Equivalent to high levels have been played two patchesrst_s2, Reaching the release of the reset signal and the clockclkThe purpose of synchronization.

references:

Understanding of "asynchronous reset, synchronous reset, asynchronous reset and synchronous release"