D trigger

D trigger is a memory function with memory function, two stable state information storage devices, which constitute a variety ofSequential circuitThe most basic logic unit is also an important unit circuit in digital logic circuits.

Therefore, D trigger has a wide range of applications in digital systems and computers. The trigger has two stable states, namely "0" and "1". Under a certain external signal, it can be flipped from one stable state to another stable state.

D trigger is integratedtriggerThe trigger composed of the door circuit. There are two types of triggers two types: level trigger and edge triggering. The former can be triggered when CP (clock pulse) = 1, and the latter is mostly triggered at the front of the CP (positive jump 0 → 1).

The second state of D trigger depends on the state of the front d side, that is, the secondary state = D. Therefore, it has two functions: setting 0 and 1.

For edge D triggers, because the circuit has maintained blocking effect during the CP = 1 period, during the CP = 1 period, the data state of the D -end changes will not affect the output state of the trigger.

D trigger is widely used, available for useDigital signalStocking, displacementRegister, Frequency and waveform generator.

1. Division circuit design D trigger to perform simulation verification

1. New project

Click FILE-> New Project Wizard ...

Specify the preservation path and file name

Use AC620 development board here

EDA tools-simulation selects NONE and uses waveform file simulation

Click Finish to complete the creation.

2. Create a schematic file

Click FILE-> New-> Block Diagram/Schematic File

Enter NAND2, the corresponding two inputs and non -door on the right will appear, add 4 with the door NAND2 and 1 non -door NOT in turn

The input and output tools of the toolbar, and the connection tool design as shown below

Save circuit diagram

Start analysis and synthesis, compile the schematic diagram file. If there is an error, the schematic diagram needs to be modified.

3. Create VWM format waveform file

Choose CLK to modify the waveform

Compile

Select the simulation device to compile

Click Start Compilation

No warning

Waveform simulation

Seeing waveform changes is delayed.

2. Call D trigger and perform simulation verification

1. New project

Above

2. Create box file

Call D trigger

Draw effect

3. Compile the schematic file, view the hardware circuit diagram

4. Create VWM format waveform file Timely simulation

Edit wave shape

Simulation results

3. Writing a D trigger inVerilog language to perform simulation verification

1. New project

Above

2. Create a new Verilog file

Write content

// dwave is the file name
module bdlatch2(d,clk,q);
    input d;
    input clk;
    output q;

    reg q;

         always @ (posedge clk) // We use the right clock to make its sensitive signal
    begin
                 Q <= d; // When the rising edge is valid, capture D to Q
    end
endmodule

Save as BDLATCH2.V and compile

3. View generated circuit diagram

4. Use Verilog language to write code for simulation test

① Open Modelsim's new project

② Select to add existing files

Add the above .v files above

③ Create a new file

Close ADD items to the project

Double -click BDLATCH2_DB.V file

Add code

Compile

④ Configuration simulation environment

Click Simulating-> Start Simulation ...

Right -click BDLATCH2_DB to select ADD WAVE

4. Summary

The D trigger simulation results implemented by the above three methods can be found that when the D trigger is a high level, when the CLK is at the rising edge, the output Q signal will change.

5. Reference link