First, the introduction of

Protected mode segment register consists of 16 bits of the 64-bit selector and descriptor register

Segment descriptor register: storing segment descriptor

Selector: memory segment descriptor index

PS: each original segment register in real mode segment selector in a protected mode, the 80486 six (i.e., CS, SS, DS, ES, FS, GS) 80-bit segment register. Code Section still CS by the selector corresponding to representation, corresponding to the segment selector SS is still represented stack segment.

Second, Detailed

First explain the concept of

（1）Global descriptor table GDT(Global Descriptor Table) in the whole system, the global descriptor table is only a GDT (a processor corresponding to a GDT), GDT can be placed anywhere in memory, but the CPU must know the entry of the GDT, i.e. the base address discharge where, Intel designers provide a door entry address register for storing GDTR GDT, the programmer will set after the GDT somewhere in memory, the GDT can be loaded into this register via an address entry LGDT instruction from after, CPU according to the contents of this register as the entry of the GDT to access the GDT. It is stored in GDTR GDT base address and limit its length table in memory.

The GDT base address specifies the linear address space of byte 0 in the address table indicates the length of the GDT byte length value. SGDT LGDT and instructions are for loading and saving the contents of registers GDTR. Immediately after the machine power up or reset processors, the default base address is set to 0, and the length value is set to 0xFFFF. A new value must be loaded in protected mode initialization to GDTR.

（2）Segment selector(Selector) by the GDTR access the global descriptor table is the "segment selector" (real mode segment registers) to complete. It is the segment selector (the same as in the segment register with the real mode) of a 16-bit register

Segment selector includesthree parts：Descriptor index (index), TI, requested privilege level (the RPL). His in index (descriptor index) section indicates the required segment descriptor in the descriptor table position from this position can be found again in accordance with the corresponding descriptors in the descriptor table is stored in GDTR base address. Then the segment descriptor table base address plus the logical address (SEL: OFFSET) by the OFFSET can be converted into a linear address, TI value selection sub-section of only a 0 or 0 representing the selected promoter is selected GDT , 1 representative of selectors is selected in the LDT. Request privilege level (the RPL) represents the selected sub-privilege level, a total of four privilege level (level 0, level 1, level 2, level 3).

Description of the privileged class: The task of each segment has a specific level. Whenever a program tries to access a particular segment, we have the privilege level of the program compared with the privilege level to be accessed to determine whether access to the segment. System Conventions, CPU can access the same segment privilege level or lower-level privilege level.

For example given a logical address: 21h: 12345678h converted to a linear address

. A selection sub-SEL = 21h = 0000000000100 0 01b meaning he represents: the selectors 100b select index = 4 i.e. the GDT fourth descriptor; TI = 0 representing the selected promoter is selected GDT; left rear 01b on behalf of the privileged class RPL = 1

b. OFFSET = 12345678h At this time, if the segment base GDT described fourth descriptor (Base) as 11111111h, the linear address = 11111111h + 12345678h = 23456789h

（3）LDT LDT(Local Descriptor Table) Local Descriptor Table can have a number of sheets, each task may have one. We can understand the GDT and LDT:Is a descriptor table GDT, LDT descriptor table for the two. Figure

LDT and GDT essence is the same, but LDT nested in the GDT.LDTR recording start position of the local descriptor tableWith GDTR different,LDTR content is a segment selector. Since the LDT itself is also a section of memory, is also a segment, so it has a descriptor to describe it, the descriptor is stored in the GDT, corresponding to the expression character will have a selection sub, the LDTR is loaded is such a selection sub. LDTR can be changed at any time in the procedure, by using lldt instruction. As shown above, if the load is then the LDTR points Selector 2 is a table LDT2. For example: if we want to choose the address 12345678h descriptor is the third segment in the table LDT2.

1. First LDTR to be loaded so that it points to Select2 lldt LDT2 usage instruction loaded into LDTR

2. logical address (SEL: OFFSET) SEL index = 3 when accessing the third representing the selected descriptor; TI = 1 representing the selected promoter is selected LDT, this time is LDT2 LDTR points, so that the selected LDT2 in this case the value of SEL 1Ch (in binary 11 1 00b). OFFSET = 12345678h. Logical address 1C: 12345678h

3. descriptor selected by the SEL, the OFFSET is obtained from the linear address of the descriptor base address (Base) plus, for example, a base address 11111111h, the linear address = 11111111h + 12345678h = 23456789h

4. At this time, if more LDT1 want to access the third descriptor, as long as the instruction using the selected sub lldt charged Selector 1 can then perform a two steps 2,3 (and because the LDTR points to LDT1)

Since each process has its own set of program segment, the data segment, a stack segment, with the Local Descriptor Table can process each block, data segment, a stack segment packaged together, can be achieved as long as the change LDTR access to segment different processes.

When a task switch, the processor descriptor segment selector and new tasks LDT will automatically load into the LDTR. After resetting the processor or machine power, and the base address of the segment selector set to 0 by default, the segment length is set to 0xFFFF.

Third, examples of (very useful for understanding)

1: Access GDT

When TI = 0 indicates when the segment descriptor in GDT, as shown above:

① start GDTR obtained GDT base address register.

② Then GDT segment selector to a high position index 13 to the descriptor worth.

③ descriptor identifier comprises a base address of the segment, length limit, priority and other attributes, which give a starting address (base address) of the segment, and then adding an offset to the base address obtained last address yyyyyyyy only linear address.

2: Access LDT

TI = 1 segment descriptor indicates when the LDT, as shown above:

① or start GDTR obtained GDT base address register.

② acquisition position index (high LDTR 13) from where the segment LDTR LDT register.

③ In this position index obtained LDT descriptor in the GDT to obtain LDT segment base.

④ obtained from LDT descriptor segment 13 position with a high index segment selector.

⑤ descriptor identifier comprises a base address of the segment, length limit, priority and other attributes, which give a starting address (base address) of the segment, and then adding an offset to the base address obtained last address yyyyyyyy only linear address.

Spread

In addition to GDTR, LDTR thereIDTR and TR

(1) Interrupt Descriptor Table Register IDTR

Similar effect and the GDTR, IDTR register for storing an interrupt descriptor table IDT 32-bit linear base address and length values ​​in Table 16. SIDT LIDT and instructions are for loading and saving the contents of registers IDTR. Immediately after the machine power up or reset processors, the default base address is set to 0, and the length value is set to 0xFFFF.

(2) task register TR

TRIt is used to address a specific task state segments(Task State Segment, TSS). TSS contains important information about the current mission.

TR registers for the current task segment TSS segment selector 16, 32-bit base address, 16-bit descriptor length and attribute values. It is a reference to the GDT TSS descriptor type. LTR and STR instructions are part of the segment selector for loading and saving TR registers. When using the LTR instruction loaded into the task register selector, described in the TSS segment base address character, Restriction lengths and descriptors attributes are automatically loaded into the task register. When performing task switching, TSS processor will receive a new task descriptor segment selector and automatically loaded into the task register TR.