This article records my learning journey of RISC-V Hummingbird E203 processor
This is the second source code file that I formally read the code study
For the study of the code, I combined my own understanding to make detailed comments on the interface of each module and the key internal signals.
The original is not easy, please protect the copyright, contact the author for reprinting, and please indicate the source and mark the original link_{Thank you}~~
e203_ifu_minidec.v

/*                                                                      
 Copyright 2017 Silicon Integrated Microelectronics, Inc.                
                                                                         
 Licensed under the Apache License, Version 2.0 (the "License");         
 you may not use this file except in compliance with the License.        
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//=====================================================================
//--        _______   ___
//--       (   ____/ /__/
//--        \ \     __
//--     ____\ \   / /
//--    /_______\ /_/   MICROELECTRONICS
//--
//=====================================================================
// Designer   : Bob Hu
//
// Description:
//  The mini-decode module to decode the instruction in IFU 
//
// ====================================================================
// ========== Some notes of my own
// This module is a part of the exu_decode module that is instantiated, and the relevant information about the jump instruction is taken out, according to
// This information determines whether a PC jump is required when the current instruction is prefetched
// ==========
`include "e203_defines.v"

module e203_ifu_minidec(

  //////////////////////////////////////////////////////////////
  // The IR stage to Decoder
  input  [`E203_INSTR_SIZE-1:0] instr, //The instruction retrieved by the instruction logic is used as input and waiting for decoding
  
  //////////////////////////////////////////////////////////////
  // The Decoded Info-Bus


  output dec_rs1en, //Decoding to determine whether reg-source1 is valid, the original operands 1 and 2 of an instruction
  output dec_rs2en, //Decoding to determine whether reg-source2 is valid
  output [`E203_RFIDX_WIDTH-1:0] dec_rs1idx, //What is returned here is the address of the original operand register in the register list file
  output [`E203_RFIDX_WIDTH-1:0] dec_rs2idx, //That is to say, the registers in the cpu are individually addressed (that is, the internal bus of the cpu, independent of the system bus) into a file
                                             //The index here is the address of the original operand register on the internal bus of the cpu
  output dec_mulhsu, // mul-high-signed-unsigned rs1 is signed, rs2 is unsigned, the high 32bit of the multiplication result (64bit) is put into rd
  output dec_mul   , // mul rs1 is unsigned, rs2 is unsigned, (signed and unsigned are actually the same) the lower 32bit of the multiplication result (64bit) is put into rd
  output dec_div   , // div rs1 has a sign, rs2 has a sign
  output dec_rem   , // Take rs1 signed and rs2 signed numbers, take the remainder and send it to dr;
  output dec_divu  , // Unsigned take business and send dr
  output dec_remu  , // unsigned take the remainder and send dr

  output dec_rv32, //Indicates whether the current instruction is an rsic-v32-bit instruction or a 16-bit instruction
  output dec_bjp,  //Indicates whether the current instruction is a normal instruction or a branch instruction, indicating whether it belongs to a bxx instruction or a jxx instruction
  output dec_jal,  //Belongs to the jal instruction
  output dec_jalr, //Data jalr instruction
  output dec_bxx,  //Belong to BXX instructions, (BEQ, BNE and other conditional branch instructions)
  output [`E203_RFIDX_WIDTH-1:0] dec_jalr_rs1idx, //For the jalr instruction, it must first fetch the rs1 operand, and then add the immediate value to get the value +4 as the new pc. In order to fetch rs1, the instruction carries the address of rs1 (cpu internal index)
  output [`E203_XLEN-1:0] dec_bjp_imm             //For bxx instructions, if the conditions are met, the 12bit immediate value (signed) × 2 will be added to pc as the new pc; here is the immediate value of the decoded instruction 

  );

  e203_exu_decode u_e203_exu_decode(  // Regarding the exu_decode module, I have commented these interface signals in e203_exu_decode.v

  .i_instr(instr),
  .i_pc(`E203_PC_SIZE'b0),
  .i_prdt_taken(1'b0), 
  .i_muldiv_b2b(1'b0), 

  .i_misalgn (1'b0),
  .i_buserr  (1'b0),

  .dbg_mode  (1'b0),

  .dec_misalgn(),
  .dec_buserr(),
  .dec_ilegl(),

  .dec_rs1x0(),
  .dec_rs2x0(),
  .dec_rs1en(dec_rs1en), //  
  .dec_rs2en(dec_rs2en), // 
  .dec_rdwen(),
  .dec_rs1idx(dec_rs1idx),
  .dec_rs2idx(dec_rs2idx),
  .dec_rdidx(),
  .dec_info(),  
  .dec_imm(),
  .dec_pc(),

  
  .dec_mulhsu(dec_mulhsu),
  .dec_mul   (dec_mul   ),
  .dec_div   (dec_div   ),
  .dec_rem   (dec_rem   ),
  .dec_divu  (dec_divu  ),
  .dec_remu  (dec_remu  ),

  .dec_rv32(dec_rv32),
  .dec_bjp (dec_bjp ),
  .dec_jal (dec_jal ),
  .dec_jalr(dec_jalr),
  .dec_bxx (dec_bxx ),

  .dec_jalr_rs1idx(dec_jalr_rs1idx),
  .dec_bjp_imm    (dec_bjp_imm    )  
  );


endmodule