EEPROM, as a processor's storage device, is often mentioned. Daniel has always wanted to explain this device, and analyze it from the perspective of use.

The most commonly used EEPROM storage chip interface is the I2C of the interface. It is just that the recent project involves this type of chip. Here is an analysis and description from the perspective of software usage. The software design adopts a layered concept to ensure that it is as concise as possible, and it is convenient to change it after replacement of the device.

In-depth understanding of the use of EEPROM, EEPROM, FRAM, FM24W256 chip IIC software design uses layered concepts to ensure as simple as possible, convenient device replacement-embedded document resource-CSDN library

EEPROM use strategy

If EEPROM uses strategy problems, if you want to explain carefully, you can write a lot of content, especially for the abnormal (damage) treatment of EEPROM.

During the software design process, storage of some parameters of the power loss saves will be stored in the situation of EERPOM life to save the number of erasure as much as possible. The emergence of iron -electric memory FRAM has given the software a lot of flexibility, which not only greatly improves the number of erasable times, but also increases the speed of reading and writing. The iron -electrical memory has no page operation restrictions. Consume a lot of delay waiting time.

hardware design

The project uses the FM24W256 chip as the storage chip to complete the storage of the main parameters of the system.

What is easy to get wrong here is the connection method of the WP foot. Generally, it can be pulled or dropped, connected to the MCU tube foot, there is no need to store protection here, so receive GND

The IIC interface is pulled up and connected directly to the MCU tube foot

software design

Store some variables at any time according to the system's needs, and all variables that need to be stored can be packaged into the same structure and stored the structure. For example

extern struct FlashParagma_t
{
	Uint32_t Flag;//0x5A0FF0A5
	uint16_t DebugComFlg;
	uint16_t DeviceID;
	uint16_t delay_U48;
	uint16_t delay_U47;
	uint16_t delay_U51;
	uint16_t delay_U52;
	uint16_t delay_U56;
	uint16_t delay_U55;
	uint16_t delay_U59;
	uint16_t delay_U60;
	uint16_t delay_U63;
	uint16_t delay_U62;
	uint16_t delay_U66;
	uint16_t delay_U65;
	uint16_t delay_U69;
	uint16_t delay_U68;
	uint16_t delay_U86;
	uint16_t delay_U93;
	uint16_t delay_U100;
	uint16_t delay_U124;
	uint16_t delay_U125;
	uint16_t delay_U126;
	uint16_t delay_U127;
	uint16_t tolerance_U30;
	uint16_t tolerance_U33;
	uint32_t CheckSum;
}FlashParagma;

In the actual use process, it is only necessary to store the structure. Of course, you can copy and store a copy. As a backup parameter, the backup parameter and the actual storage location should be guaranteed to be physical isolation, and there should be no overlap address on the memory.

Code architecture analysis

As shown in the figure below, the core code architecture is shown in the figure below. The application layer program maintains the above -mentioned structure. The storage of the structure is used to call the memory read and write function. The memory read and write function is supplemented by calling the timing function of the function I2C.

Data reading

First determine the read and write address of the device, check the manual, and find it

Refer to the hardware design wiring diagram, all A0 a1 A2 is all ground, so it takes 0, and the read function is relatively simple.

Data writing

The data writing is relatively complicated. Here we need to consider compatibility with EEPROM writing. It can be used normally, regardless of the PCB panel panel installation EEPROM and FRAM, and ensure that the software can be used normally. Reference routine code.

//FM24W256

#Define FM24C_TOTAL_SIZE (32*1024) // The size of this device

 #Define fm24c_page_size (32) // The number of bytes of one page

Here is a pagination processing for FRAM. In order to be compatible with the same series of EEPROM, it is written according to paging processing.

Based on whether the first address of the writing is the page starting address and whether the length of the writing length is an integer multiple of the page length, the writing operation is performed. When the page is written, it needs to be delayed for a period of time. If the time requirements are high, this delay time can be optimized.

More detailed information routine code reference

In-depth understanding of the use of EEPROM, EEPROM, FRAM, FM24W256 chip IIC software design uses layered concepts to ensure as simple as possible, convenient device replacement-embedded document resource-CSDN library

Routine code

Use STM32Cubeide Version: 1.8.0. Here is STM32F407. Of course, you can also switch to other MCUs, or transplant the code to other MCUs.

Test instruction

The routine code realizes the number of times the number of start -ups, and the value of the structure variable from the FRAM reads the structure variables from the FRAM, determine whether the verification is correct, and restore the factory setting operation if it is incorrect. Go to Fram. Printing character as shown in the figure below

After the script code is started for the first time, the factory settings are restored, and the number of boot times will be recorded at each boot.

More detailed information routine code reference

In-depth understanding of the use of EEPROM, EEPROM, FRAM, FM24W256 chip IIC software design uses layered concepts to ensure as simple as possible, convenient device replacement-embedded document resource-CSDN library