Electronic Design Tutorial 49: 16*16LED dot matrix screen driver-74HC595 principle

I tried to use shift register cascade + 38 decoder to achieve the effect of driving 16*16 LED dot matrix screen with 3 control lines. This is the first blog about the working principle of the 74HC595 chip

Generally, a single-chip microcomputer is used to control the LED. One pin to control one LED is the most intuitive method. But it is also the dumbest method. Pins are precious resources for single-chip microcomputers. The more chip pins with the same performance, the more expensive the price. However, some peripherals take up many pins, such as LED screens. In theory, one LED needs one pin to operate, and 64 LEDs form an 8×8 screen, which requires up to 64 pins. But smart engineers will save pins and connect the LEDs in rows and columns to form a matrix. Only 16 pins are needed. If you feel that using 16 pins is a bit too much, you can consider using a shift register cascade application circuit. At least 3 pins are needed to control many LEDs, more than 64, and theoretically even infinite.

74HC595 has an 8-bit shift register and a memory, with three-state output function. The shift register and the storage register have independent clocks. Data is input to the shift register at the rising edge of the shift register clock input, and input to the storage register at the rising edge of the storage register clock input. The shift register has 1 serial shift input, 1 serial output, and 1 asynchronous low-level reset. The storage register has 1 parallel 8-bit, with three-state bus output. When enabled When OE (when it is low level), the data of the storage register is output to the bus.
Many manufacturers produce such chips (such as TI, NXP, etc.), although they are all 595 chips, but the names are slightly different, such as 74lv595, 74ls595, 74hc595, etc., in addition , Pin names, speeds, voltages, circuits, input and output levels, etc., are also different. For details, please refer to the corresponding component manual. One of the biggest features of the 595 chip is that it can be cascaded. At least 3 IO ports of the controller can be used to control many 595s. As long as the circuit design is reasonable, cascading hundreds of pieces is not a problem. Imagine if it is used to drive relays, LEDs and other devices that can be controlled by one pin, cascading 100 pieces of 595, each piece can drive 8 devices, a total of 800 can be driven, and only 3 IO ports of the controller are occupied

Pin	name	Alias	Circuit board silk screen	Features	Description
15,1-7	QA-QH	Q0-Q7		Parallel data output
9	QH’	Q7S		Serial data output	When the data in the shift register overflows, the 1bit data stored first is squeezed out from this pin. Often used for cascading.
10	$\overline{\text{SRCLR}}$	$\overline{\text{MR}}$	nRESET	Reset	Low level is effective, you can clear the data in the shift register.
11	SRCLK	SHCP	CLOCK	Shift register clock input	At the rising edge, squeeze new 1bit data into the shift register
12	RCLK	STCP	LANCH	Storage register clock input	At the rising edge, all 8bit data of the shift register is stored in the storage register.
13	$\overline{\text{OE}}$			Output enable	Active low, output 8bit data in storage register to QA-QH
14	SER	DS	DI	Data serial input	Data is input bit by bit on this pin.
8,16	GND,VCC			Ground, power

Generally, in order to explain the working principle of 74HC595, it is necessary to explain its truth table and timing diagram. But neither of these shows the working logic of shift registers and storage registers, and some of the information is not practical, so this article does not explain the truth table and timing diagram, only the following figure to explain the working principle of 74HC595, and sort out the key point.

1: On the rising edge of SRCLK, the data from SER can be stored in the shift register. The shift register has only 8 bits. If the data overflows, the overflowed data is output from QH' (shown by the hollow arrow in the figure).
2: At the rising edge of RCLK, all 8-bit data of the shift register are transferred to the storage register (shown by the dotted line in the figure). If OE is low at this time, 8-bit data will be output in parallel.
3: SRCLR can clear the shift register when it is low. Generally, it is pulled low when it is safely powered on for the first time, and set high at other times. OE allows output at low level and tri-state output at high level. The tri-state is neither a high level nor a low level, and is called a high impedance state. In practical applications, OE is often set to low level.
4: Assuming that the data from the control chip is ABCD EFGH, each letter represents 1 bit of data, either 0 or 1. Then the high-order number A will be stored in the shift register first, the first data will be output from QH, and the eighth stored data will be output from QA.

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