Detect the 11101 sequence and draw a state transition diagram.

1. State transition diagram (Mealy type) Input/Output

2. Code

Create fsm11101 file

//Two-stage
module fsm11101(
	input		wire		sclk,
	input		wire		rst_n,
	input		wire		A,
	output	    reg			k
);

parameter		s1=6'b000001;
parameter		s2=6'b000010;
parameter		s3=6'b000100;
parameter		s4=6'b001000;
parameter		s5=6'b010000;
parameter		s6=6'b100000;

reg 	[5:0]		state;
always	@(posedge	sclk or negedge	rst_n)
			if(rst_n==1'b0)
					state<=s1;
			else
					case(state)
						s1:
								if(A==1'b1)
										state<=s2;
								else
										state<=s1;
						
						s2:
								if(A==1'b1)
										state<=s3;
								else
										state<=s1;
						
						s3:
								if(A==1'b1)
										state<=s4;
								else
										state<=s1;
										
						s4:
								if(A==1'b1)
										state<=s4;
								else
										state<=s5;
										
						s5:
								if(A==1'b1)
										state<=s6;
								else
										state<=s1;
						
						s6:state<=s1;
						default:state<=s1;
				endcase

always @(posedge	sclk	or	negedge	rst_n)
		if(rst_n==1'b0)
					k<=1'b0;
		else if(state==s5 && A==1'b1)
					k<=1'b1;
		else
					k<=1'b0;
					
endmodule					

3.testbeach

Create tb_fsm11101 file

`timescale  1ns/1ns
module tb_fsm11101;
		reg		sclk,rst_n;
		reg		a_in;
		wire	k_out;

initial	begin
		sclk=0;
		rst_n=0;
		#100;
		rst_n=1;
end

initial  begin
		#200;
		rand_bit();
end
always #10 sclk<=~sclk;

fsm11101  fsm11101_inst(
		.sclk		(sclk),
		.rst_n	    (rst_n),
		.A			(a_in),
		.k			(k_out)
);

task rand_bit();
		integer i;
		begin
	  		for(i=0;i<255;i=i+1)
	  		begin
	  	  		@(posedge sclk);
	  	  		 a_in<={$random} %2; //Generate 0--1
	  	  end
	  end
endtask

endmodule
		

4. Simulation (ModelsimSE-64 simulation)

Build simulation script run.do file (use script file to write more convenient)

quit -sim
.main	clear

 # 
vlib		./lib/
vlib		./lib/work_a/
vlib		./lib/design/

 #MAP Map base_space to ./lib/work_a/ base_space and design are two logic libraries 
vmap		base_space ./lib/work_a/
vmap    design  ./lib/design/

 #Compile-work Compile tb_fsm11101.v in this folder into the base_space logic library
vlog		-work base_space		./tb_fsm11101.v
 #.. is to turn up a folder, see the design folder, compile all the .v files in this folder to the logic library of design
vlog		-work	design				./../design/*.v

 #start up 
 #-t The accuracy of the event to run the simulation is ns
 #-L is a keyword for linking libraries
vsim		-t ns -voptargs=+acc	-L base_space -L design base_space.tb_fsm11101

 #Add virtual structure
virtual type {
{01 s1}
{02 s2}
{04 s3}
{08 s4}
{10 s5}
{20 s6}
} vir_new_signal

#add wave	-divider{tb_sim}
add wave	tb_fsm11101/*

#add wave	-divider{des}
 #Top level + instantiated name/* where * is a wildcard, matching all signals 
add wave	tb_fsm11101/fsm11101_inst/*

 #Create (vir_new_signal) type signal, convert state signal to new_state signal
virtual	function {(vir_new_signal)tb_fsm11101/fsm11101_inst/state} new_state
add wave	-color red   tb_fsm11101/fsm11101_inst/new_state

run 1us

Notes:

These three statements are to convert the state signal into a new_state signal. You can clearly see s1, s2...s6 in the figure below

#Add virtual structure
virtual type {
{01 s1}
{02 s2}
{04 s3}
{08 s4}
{10 s5}
{20 s6}
} vir_new_signal

#Create (vir_new_signal) type signal, convert state signal to new_state signal
virtual    function {(vir_new_signal)tb_fsm11101/fsm11101_inst/state} new_state

add wave    -color red   tb_fsm11101/fsm11101_inst/new_state
 

5. Results